AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 265

• Manufacturer Part Number: AT91SAM7X128B-AU
• Description: IC MCU 128KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 55 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 55MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 28-8. Peripheral Deselection
28.6.3.8
28.6.4
6120I–ATARM–06-Apr-11
Write SPI_TDR
Write SPI_TDR
Write SPI_TDR
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
TDRE
TDRE
TDRE
SPI Slave Mode
Mode Fault Detection
A
A
A
DLYBCT
DLYBCT
DLYBCT
Figure 28-8
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be con-
figured in open drain through the PIO controller, so that external pull up resistors are needed to
guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and
the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Con-
trol Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
CSAAT = 0
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
shows different peripheral deselection cases and the effect of the CSAAT bit.
PCS = A
A
B
A
SAM7X512/256/128 Preliminary
A
A
A
DLYBCT
DLYBCT
DLYBCT
CSAAT = 1
DLYBCS
DLYBCS
PCS = B
PCS = A
A
A
PCS = A
DLYBCS
A
A
B
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