AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 678

IC MCU 128KB FLASH 100LQFP

AT91SAM7X128B-AU

Manufacturer Part Number
AT91SAM7X128B-AU
Description
IC MCU 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7X128B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
55 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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682
Version
6120E
6120D
6120C
6120B
6120A
SAM7X512/256/128 Preliminary
Comments
04-Apr-06
The following errata have been added:
Section 41.3.3.2 ”EMAC: Possible Event Loss when Reading EMAC_ISR”
Section 41.3.3.3 ”EMAC: Possible Event Loss when Reading the Statistics Register Block”
Section 41.3.7.3 ”SPI: SPCK Behavior in Master Mode”
Section 41.3.4.1 ”PIO: Leakage on PB27 -
03-Feb-06
Section 41. ”SAM7X512/256/128 Errata”
Device package/product number changed
Section 41.3.3 ”Ethernet MAC (EMAC)”
The sections listed below have been added to the Errata:
Section 41.3.5 ”Pulse Width Modulation Controller (PWM)”
Section 41.3.7 ”Serial Peripheral Interface (SPI)”
Section 41.3.8 ”Synchronous Serial Controller (SSC)”
Section 41.3.9 ”Two-wire Interface (TWI)”
Section 41.3.10 ”Universal Synchronous Asynchronous Receiver Transmitter (USART)”
26-Oct-05
Replaced
17-Oct-05
Updated product functionalities in
on page
Corrected PLL output range maximum value in
Section 18.3.2.1 “Internal Memory Mapping” on page 95
Characteristics,” on page
Updated information in Power Supplies on page 9
Updated field Part Number in
Updated Chip ID in
Removed references to PGMEN2 in
Updated “ARCH: Architecture Identifier” in Debug Unit with new values for AT91SAM7XCxx series and
AT91SAM7Xxx series.
Updated CAN bit timing configuration in
and in
Added
Updated AT91SAM7X Ordering information.
10-Oct-05
Section 36.8.6 “CAN Baudrate Register” on page
Section 38.8.4 “EMAC Characteristics” on page
28, and Figure 11-1 on page 27
Section 29. “Two-wire Interface (TWI)” on page
Section 9.5 “Debug Unit” on page 28
621.
Section 12.5.5 “ID Code Register” on page
“Features” on page
Section 20. “Fast Flash Programming Interface (FFPI)” on page
RMII mode is not functional
Section 36.6.4.1 “CAN Bit Timing Configuration” on page 510
PB30”: worst case leakage changed to 9 µA
Section 9.2 “Clock Generator” on page
1,
628.
Figure 2-1 on page
543.
and
and in
281.
Table 38-12, “Phase Lock Loop
Section 12.5.3 “Debug Unit” on page
55.
4,
Section 9.5 “Debug Unit”
26,
Figure 18-3
119.
6120I–ATARM–06-Apr-11
48.
in
Change
Request
Ref.
#2455
#2605
#1767
05-516
05-456
05-491
05-472
05-464
05-459
05-419
05-469
05-470
First issue

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