AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 665

IC MCU 128KB FLASH 100LQFP

AT91SAM7X128B-AU

Manufacturer Part Number
AT91SAM7X128B-AU
Description
IC MCU 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7X128B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
55 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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41.6
41.6.1
41.6.1.1
41.6.2
41.6.2.1
41.6.2.2
41.6.3
41.6.3.1
6120I–ATARM–06-Apr-11
AT91SAM7X256/128 Errata - Rev. C Parts
Embedded Flash Controller (EFC)
Ethernet MAC (EMAC)
Peripheral Input/Output (PIO)
EFC: Embedded Flash Access Time 2
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26
Refer to
Note:
The embedded Flash maximum access time is 20 MHz (instead of 30 MHz at zero Wait State
(FWS = 0).
The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55
MHz). Above 48.1 MHz and up to 55MHz, two Wait States (FWS = 2) are required.
Set the number of Wait States (FWS) according to the frequency requirements described in this
errata.
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the volt-
age of the I/O stabilizes at VPull-up.
Vpull-up
VPull-up Min
VDDIO - 0.65 V
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7X256 Revision C chip ID is 0x275B 0942.
AT91SAM7X128 Revision C chip ID is 0x275A 0742.
Section 41.1 “Marking” on page
VPull-up Max
VDDIO - 0.45 V
SAM7X512/256/128 Preliminary
635.
665

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