AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 521

• Manufacturer Part Number: AT91SAM7X128B-AU
• Description: IC MCU 128KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 55 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 55MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.7.3
36.7.3.1
36.7.3.2
Figure 36-11. Receive Mailbox
Note:
6120I–ATARM–06-Apr-11
(CAN_MSRx)
(CAN_MSRx)
CAN_MDHx)
(CAN_MCRx)
(CAN_MDLx
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler
instruction.
CAN BUS
CAN Controller Message Handling
MRDY
Receive Handling
MTCR
Simple Receive Mailbox
MMI
Reading CAN_MDHx & CAN_MDLx
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the
first message received is stored in the mailbox data register. In Receive with Overwrite Mode,
the last message received is stored in the mailbox.
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been config-
ured. Message ID and Message Acceptance Mask must be set before the Receive Mode is
enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first message is received. When the first message has been accepted by the
mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.
Message data are stored in the mailbox data register until the software application notifies that
data processing has ended. This is done by asking for a new transfer command, setting the
MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by
the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx
register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents
from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx regis-
ter. See
Message 1
Figure
36-11.
Reading CAN_MSRx
Message 2 lost
Message 1
Writing CAN_MCRx
SAM7X512/256/128 Preliminary
Message 3
Message 3
Message ID = CAN_MIDx
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