AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 45
![MCU CAP7 FPGA 225LFBGA](/photos/12/32/123241/225-lfbga_sml.jpg)
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 11-4. Dual Master Mode
11.3.4
Figure 11-5. Read/Write timing for Single Master Mode
8549A–CAP–10/08
CAP7E
AHB
FPIF_SCLK
HWDATA
Transfer Timing
HRDATA
HREADY
HADDR
CAP7E AHB CLK
Ctrl
A
C
S0
S1
t1
CAP7E FSM
D
Shifter
As mentioned previously, the number of clocks per transfer and therefore the effective trans-
fer speed depends upon the two ratios between the CAP7E and FPGA AHB clock frequen-
cies and the FPIF_SCLK. In addition, the Master Mode selection affects the effective transfer
speed as follows:
•
•
Figure 11-5
•
•
Single Master Mode: Takes 4 FPIF_SCLK cycles to transfer data for 1 AHB interface.
See t2 and t3 on
Dual Master Mode: Takes 8 FPIF_SCLK cycles to transfer all AHB data of 2 AHB
interfaces.
t1: Time for a standard 2 cycles AHB
t2: Time to transfer the request to FPGA (4 cycles single AHB interface, 8 cycles dual
AHB interface).
Serial Data to FPGA
shows all the timing for a transfer between the CAP7E and the FPGA.
t2
FPIF Serial Clock
Control
Figure 11-5
S0
S1
t6
t3
Serial Data to CAP7E
below.
t4
FPGA FSM
Shifter
FPGA AHB CLK
Response
t5
D
S0
S1
FPGA
AT91CAP7E
AHB
45
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