AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 491

MCU CAP7 FPGA 225LFBGA

AT91CAP7E-NA-ZJ

Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Datasheets

Specifications of AT91CAP7E-NA-ZJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91CAP7E-NA-ZJ
Manufacturer:
Atmel
Quantity:
10 000
33.10.4
33.10.4.1
Timings are given assuming a capacitance load on data, control and address pads.
Table 33-21. Capacitance Load
In the following tables, t
33.10.4.2
Table 33-22. SMC Read Signals - NRD Controlled (READ_MODE= 1)
Table 33-23. SMC Read Signals - NCS Controlled (READ_MODE= 0)
8549A–CAP–10/08
Supply
3.3V
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
8
9
10
11
SMC Timings
Capacitance
Read Timings
Parameter
VDDIO supply
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
A2 - A25 Valid before NRD High
NCS low before NRD High
NRD Pulse Width
Parameter
VDDIO supply
Data Setup before NCS High
Data Hold after NCS High
Data Setup before NCS High
Data Hold after NCS High
NBS0/A0, NBS1, NBS2/A1, NBS3,
HOLD or NO HOLD SETTINGS (ncs rd hold … 0, ncs rd hold = 0)
HOLD or NO HOLD SETTINGS (nrd hold … 0, nrd hold =0)
CPMCK
MAX
50pF
NO HOLD SETTINGS (ncs rd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
HOLD SETTINGS (ncs rd hold … 0)
is MCK period.
HOLD SETTINGS (nrd hold … 0)
(nrd setup + nrd pulse)* t
STH
50pF
(nrd setup + nrd pulse - ncs rd
nrd pulse * t
Min
setup) * t
Corner
3.3V
TBD
TBD
TBD
TBD
TBD
3.3V
TBD
TBD
TBD
TBD
Min
CPMCK
CPMCK
+ TBD
+ TBD
CPMCK
MIN
0 pF
+
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AT91CAP7E
491

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