AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 55
![MCU CAP7 FPGA 225LFBGA](/photos/12/32/123241/225-lfbga_sml.jpg)
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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12. ARM7TDMI Processor Overview
12.1
12.2
12.2.1
12.2.2
12.2.3
8549A–CAP–10/08
Overview
ARM7TDMI Processor
Instruction Type
Data Type
ARM7TDMI Operating Mode
The ARM7TDMI core executes both the 32-bit ARM
ing the user to trade off between high performance and high code density.The ARM7TDMI
processor implements Von Neuman architecture, using a three-stage pipeline consisting of
Fetch, Decode, and Execute stages.
The main features of the ARM7tDMI processor are:
For further details on ARM7TDMI, refer to the following ARM documents:
ARM Architecture Reference Manual (DDI 0100E)
ARM7TDMI Technical Reference Manual (DDI 0210B)
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be
aligned to four-byte boundaries and half words to two-byte boundaries.
Unaligned data access behavior depends on which instruction is used where.
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:
Mode changes may be made under software control, or may be brought about by external inter-
rupts or exception processing. Most application programs execute in User mode. The non-user
• ARM7TDMI Based on ARMv4T Architecture
• Two Instruction Sets
• Three-Stage Pipeline Architecture
– ARM
– Thumb
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
User: The normal ARM program execution state
FIQ: Designed to support high-speed data transfer or channel process
IRQ: Used for general-purpose interrupt handling
Supervisor: Protected mode for the operating system
Abort mode: Implements virtual memory and/or memory protection
System: A privileged user mode for the operating system
Undefined: Supports software emulation of hardware coprocessors
®
High-performance 32-bit Instruction Set
®
High Code Density 16-bit Instruction Set
®
and 16-bit Thumb
®
AT91CAP7E
instruction sets, allow-
55
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