LH75411N0Q100C0;55 NXP Semiconductors, LH75411N0Q100C0;55 Datasheet - Page 41

• Manufacturer Part Number: LH75411N0Q100C0;55
• Description: IC ARM7 BLUESTREAK MCU 144LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH75411N0Q100C0;55

• Package / Case: 144-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 84MHz
• Connectivity: EBI/EMI, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH75
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 84 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4330; 935285046557

System-on-Chip
MEMORY CONTROLLER WAVEFORMS
Static Memory Controller Waveforms
External Static Memory Write, with one Wait State. Fig-
ure 9 shows the waveform and timing for an External
Static Memory Write, with two Wait States. Figure 10
shows the waveform and timing for an External Static
Memory Read, with one Wait State.
by an external device to extend the wait time during a
memory access. The SMC samples nWAIT at the
beginning of at the beginning of each system clock
cycle. The system clock cycle in which the nCSx signal
is asserted counts as the first wait state. See Figure 11.
The SMC recognizes that nWAIT is active within 2
clock cycles after it has been asserted. To assure that
the current access (read or write) will be extended by
nWAIT, program at least two wait states for this bank of
Preliminary data sheet
Figure 8 shows the waveform and timing for an
The SMC supports an nWAIT input that can be used
XTAL32
XTAL14
LREG
nPOR
VDD
PLL
VDDmin
VDDCmin
tLREG
tOSC14
tOSC32
Figure 7. Power-up Stabilization
tPORH
NXP Semiconductors
Rev. 01 — 16 July 2007
memory. If N wait states are programmed, the SMC
holds this state for N system clocks or until the SMC
detects that nWAIT is inactive, whichever occurs last.
As the number of wait states programmed increases,
the amount of delay before nWAIT must be asserted
also increases. If only 2 wait states are programmed,
nWAIT must be asserted in the clock cycle immediately
following the clock cycle during which the nCSx signal
is asserted. Once the SMC detects that the external
device has deactivated nWAIT, the SMC completes its
access in 3 system clock cycles.
ing nCSx and asserting nWAIT is:
measurements are made from the Address Valid point
and HCLK is an internal signal, shown for reference only.
The formula for the allowable delay between assert-
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
The signal tIDD is shown without a setup time, as
LH75401/LH75411
LH754xx-100
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