LH75411N0Q100C0;55 NXP Semiconductors, LH75411N0Q100C0;55 Datasheet - Page 54

• Manufacturer Part Number: LH75411N0Q100C0;55
• Description: IC ARM7 BLUESTREAK MCU 144LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH75411N0Q100C0;55

• Package / Case: 144-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 84MHz
• Connectivity: EBI/EMI, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH75
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 84 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4330; 935285046557

LH75401/LH75411
54
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
NOTE:
*
SYNCHRONIZATION)
*
(INTERNAL)
APBPeriphClkCtrl1:LCD
ClkPrescale:LCDPS
(SHOWN FOR REFERENCE)
Source is RCPC.
SYNCHRONIZATION
(LCD VIDEO DATA)
CLCDCLK
(HORIZONTAL
(VERTICAL
LCDVD[11:0]
LCDSPS
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
PULSE)
LCDLP
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0]
(DELAYED FOR
AD-TFT, HR-TFT)
LCDDCLK
(PANEL CLOCK)
Timing2:PCD
Timing2:BCD
Timing2:IPC
Timing2:CPL
LCDEN
(DATA ENABLE)
LCDVD[11:0]
LCDCLS
LCDREV
LCDPS
Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram
Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
1.5 µs - 4 µs
Timing0:HSW
Timing1:VSW
Timing1:CLSDEL
Timing1:LPDEL
Timing0:HSW +
Timing0: HBP
NXP Semiconductors
Rev. 01 — 16 July 2007
1 LCDDCLK
1 LCDDCLK
001
002 003 004 005 006 007 008
1 AD-TFT or HR-TFT HORIZONTAL LINE
001
002 003 004 005 006
Timing2:CLSDEL2
PIXEL DATA
Timing1:REVDEL
320
317
318
319 320
Preliminary data sheet
System-on-Chip
LH754xx-80
LH754xx-81