ST72F321BAR6T6 STMicroelectronics, ST72F321BAR6T6 Datasheet - Page 123
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ST72F321BAR6T6
Manufacturer Part Number
ST72F321BAR6T6
Description
MCU 8BIT 32KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321BK6T6.pdf
(187 pages)
Specifications of ST72F321BAR6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5582
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F321BAR6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
I
I
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
2
2
EVF
C BUS INTERFACE (Cont’d)
C STATUS REGISTER 1 (SR1)
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
– SB=1 (Start condition generated in Master
– AF=1 (No acknowledge received after byte
– STOPF=1 (Stop condition detected in Slave
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Mas-
7
while ACK=1)
mode)
transmission)
mode)
condition detected)
ter mode.
ADD10
TRA
BUSY
BTF
ADSL
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
M/SL
Figure
SB
0
67.
1: Data byte transmitted
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note:
– The BUSY flag is NOT updated when the inter-
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– Following a byte transmission, this bit is set after
– Following a byte reception, this bit is set after
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
face is disabled (PE=0). This can have conse-
quences when operating in Multimaster mode;
i.e. a second active I
transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
consists of checking that the I
fore enabling the I
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
2
C Multimaster cell.
2
C master commencing a
Figure
2
C is not busy be-
67). BTF is
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