ST72F321BAR6T6 STMicroelectronics, ST72F321BAR6T6 Datasheet - Page 27
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ST72F321BAR6T6
Manufacturer Part Number
ST72F321BAR6T6
Description
MCU 8BIT 32KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321BK6T6.pdf
(187 pages)
Specifications of ST72F321BAR6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5582
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F321BAR6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
t
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
t
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
(see
Figure 15. RESET Sequences
w(RSTL)out
w(RSTL)out
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
“OPERATING CONDITIONS” on page
V
V
IT+(LVD)
IT-(LVD)
Figure
.
(see short ext. Reset in
RUN
V
15). Starting from the external RE-
DD
ACTIVE PHASE
DD
RESET
LVD
is over the minimum
OSC
Figure
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
t
t
frequency.
w(RSTL)out
h(RSTL)in
RUN
15), the
140)
ACTIVE
PHASE
SHORT EXT.
RESET
DELAY
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
t
Power-On RESET
Voltage Drop RESET
h(RSTL)in
t
w(RSTL)out
<V
RUN
IT-
(falling edge) as shown in
WATCHDOG UNDERFLOW
ACTIVE
PHASE
LONG EXT.
RESET
w(RSTL)out
DD
<V
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
RUN
DD
IT+
.
larger than t
ACTIVE
(rising edge) or
PHASE
WATCHDOG
RESET
t
w(RSTL)out
Figure
Figure
DD
g(VDD)
15.
supply
RUN
27/187
CPU
15.
to
)