ST72F321BAR6T6 STMicroelectronics, ST72F321BAR6T6 Datasheet - Page 13
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ST72F321BAR6T6
Manufacturer Part Number
ST72F321BAR6T6
Description
MCU 8BIT 32KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321BK6T6.pdf
(187 pages)
Specifications of ST72F321BAR6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5582
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F321BAR6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See See “I/O PORTS” on page 46. and
ISTICS
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see
more details.
4. On the chip, each I/O port may have up to 8 pads:
– Pads that are not bonded to external pins are forced by hardware in input pull-up configuration after re-
5.
6.
pins to ground.
48 33
49 34 17 PA4 (HS)
50 35
51 36 18 PA6 (HS)/SDAI
52 37 19 PA7 (HS)/SCLI
53 38 20 V
54 39 21 RESET
55
56
57 40 22 V
58 41 23 OSC2
59 42 24 OSC1
60 43 25 V
61 44 26 PE0/TDO
62
63
64
set. The configuration of these pads must be kept at reset state to avoid added current consumption.
Pin n°
Pull-up always activated on PE2 see limitation
It is mandatory to connect all available V
1
-
-
-
-
for more details.
27 PE1/RDI
-
-
-
-
-
-
Section 1 DESCRIPTION
V
PA5 (HS)
EVD
TLI
PE2
PE3
SS_1
PP
SS_2
DD_2
/ ICCSEL
Pin Name
3)
3)
I/O C
I/O C
I/O C
I/O C
I/O C
I/O
I/O C
I/O C
I/O C
I/O C
S
S
S
I
I
I
and
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
C
Level
T
T
T
T
T
T
T
T
T
T
Section 12.5 CLOCK AND TIMING CHARACTERISTICS
HS
HS
HS
HS
DD
X
X
X
X
X
X
X
and V
X
X
X
X
X
X
Section
Input
REF
X
Port
pins to the supply voltage and all V
15.1.8.
Section 12.8 I/O PORT PIN CHARACTER-
X
Output
X
X
T
T
X
X
X
5)
X
X
X
X
X
X
5)
function
Digital Ground Voltage
Port A4
Port A5
Port A6
Port A7
Must be tied low. In flash program-
ming mode, this pin acts as the pro-
gramming voltage input V
Section 12.9.2
voltage must not be applied to ROM
devices
Top priority non maskable interrupt.
External voltage detector
Top level interrupt input pin
Digital Ground Voltage
Resonator oscillator inverter output
External clock input or Resonator os-
cillator inverter input
Digital Main Supply Voltage
Port E0
Port E1
Port E2
Port E3
reset)
(after
Main
SCI Transmit Data Out
SCI Receive Data In
I
I
2
2
C Data
C Clock
Alternate function
for more details. High
1)
1)
SS
PP
and V
. See
13/187
SSA
for
DD