ST72F321BAR6T6 STMicroelectronics, ST72F321BAR6T6 Datasheet - Page 128

MCU 8BIT 32KB FLASH/ROM 64-LQFP

ST72F321BAR6T6

Manufacturer Part Number
ST72F321BAR6T6
Description
MCU 8BIT 32KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F321BAR6T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5582

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F321BAR6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F321BAR6T6
Manufacturer:
ST
0
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
10.8 10-BIT A/D CONVERTER (ADC)
10.8.1 Introduction
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 69. ADC Block Diagram
128/187
f
CPU
AIN0
AIN1
AINx
DIV 2
DIV 4
ANALOG
MUX
EOC SPEED ADON
4
ADCDRH
0
1
f
ADC
0
ADCDRL
CH3
D9
CH2
D8
10.8.2 Main Features
The block diagram is shown in
CH1
D7
10-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
0
CH0
D6
0
D5
ADCCSR
0
D4
0
ANALOG TO DIGITAL
D3
CONVERTER
0
D2
0
Figure
D1
69.
D0

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