STM32F103R8H7 STMicroelectronics, STM32F103R8H7 Datasheet - Page 92
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STM32F103R8H7
Manufacturer Part Number
STM32F103R8H7
Description
MCU 32BIT 64K FLASH 64BGA
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F103R8H6.pdf
(99 pages)
Specifications of STM32F103R8H7
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LFBGA
Processor Series
STM32F103x
Core
ARM Cortex M3
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F103R8H7
Manufacturer:
STMicroelectronics
Quantity:
10 000
Revision history
8
92/99
Revision history
Table 60.
01-jun-2007
20-Jul-2007
Date
Document revision history
Revision
1
2
Initial release.
Flash memory size modified in
BGA100 pins added to
definitions.
ballout
T
AC timing
t
characteristics. I
characteristics.
Sample size modified and machine model removed in
discharge
Number of parts modified and standard reference updated in
latch-up. 25 °C and 85 °C conditions removed and class name modified
in
added to
added to
Figure 31: I2C bus AC waveforms and measurement circuit
Figure 30: Recommended NRST pin protection
Notes removed below
I
in Run and Sleep
t
characteristics.
In
endurance and data retention for T
T
V
voltage. Document title changed.
section modified.
Figure 13: Power supply scheme
Features on page 1
SU(LSE)
DD
STAB
A
HSE
BG
Table 33: Electrical
Table 29: Flash memory endurance and data
= 25 °C removed.
Doc ID 13587 Rev 13
typical values changed in
changed to V
, V
changed to T
added.
REF+
changed to t
Table 35: I/O static
Table 38: NRST pin
diagram. V
(ESD).
Figure 3: STM32F103xx performance line LFBGA100
value, t
DD(HSI)
modes.
REFINT
LSE
list optimized. Small text changes.
lat
SU(HSE)
BAT
sensitivities. R
Table
in
and f
Table 5: Medium-density STM32F103xx pin
max value added to
in
ranged modified in
Figure 22: Low-speed external clock source
Table 39: TIMx characteristics
Table 12: Embedded internal reference
TRIG
9,
characteristics. R
in
characteristics.
Table 11: Maximum current consumption
Changes
Table
Note
Table 22: HSE 4-16 MHz oscillator
added to
modified.
Controller area network (CAN)
A
= 85 °C added, data retention for
PU
8,
38,
STM32F103x8, STM32F103xB
Note
and R
Table
Table 46: ADC
Table 24: HSI oscillator
Power supply
5,
PD
PU
44.
Note
corrected.
retention, typical
min and max values
min and max values
7,
Electrostatic
Note 9
modified.
schemes.
and
Static
and