ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 31

MCU 16BIT 256K FLASH 144PQFP

ST10F269Z2Q6

Manufacturer Part Number
ST10F269Z2Q6
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheets

Specifications of ST10F269Z2Q6

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Controller Family/series
ST10
No. Of I/o's
111
Ram Memory Size
12KB
Cpu Speed
40MHz
No. Of Timers
5
Embedded Interface Type
CAN, SSC, USART
Rohs Compliant
Yes
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-4833

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When the ST10F269-T3 has entered BSL mode, the following configuration is automatically set (values
that deviate from the normal reset values, are marked):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST10F269-T3 can return the identification Byte.
Even if the internal Flash is enabled, no code can
be executed out of it.
The hardware that activates the BSL during reset
may be a simple pull-down resistor on P0L.4 for
systems that use this feature upon every
hardware reset.
A switchable solution (via jumper or an external
signal)
only temporarily use the bootstrap loader (see
Figure 6).
After
ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL.
Figure 6 : Hardware Provisions to Activate the BSL
Watchdog Timer:
Context Pointer CP:
Stack Pointer SP:
Register S0CON:
Register S0BG:
sending
POL.4
can
be
the
used
identification
Disabled
FA00h
FA40h
8011h
Acc. to ‘00’ Byte
for
R
8kΩ
Circuit 1
POL.4
systems
Byte
that
the
Register SYSCON:
Register STKUN:
Register STKOV:
Register BUSCON0:
P3.10 / TXD0:
DP3.10:
5.6.2 - Memory Configuration After Reset
The configuration (and the accessibility) of the
ST10F269-T3’s memory areas after reset in
Bootstrap-Loader mode differs from the standard
case. Pin EA is not evaluated when BSL mode is
selected, and accesses to the internal Flash area
are partly redirected, while the ST10F269-T3 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses
ROMless devices.
The code in the Boot-ROM is not an invariant
feature of the ST10F269-T3. User software
should not try to execute code from the internal
Flash area while the BSL mode is still active, as
these fetches will be redirected to the Boot-ROM.
The Boot-ROM will also “move” to segment 1,
when the internal Flash area is mapped to
segment 1 (see Figure 7).
POL.4
will
return
0E00h
FA40h
FA0Ch 0<->C
acc. to startup configuration
‘1’
‘1’
External
Signal
undefined
BSL
R
8kΩ
Circuit 2
Normal Boot
POL.4
ST10F269-T3
values
31/162
on

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