MC9S08AW16MFGE Freescale Semiconductor, MC9S08AW16MFGE Datasheet - Page 29

• Manufacturer Part Number: MC9S08AW16MFGE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW16MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.3.3
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 bus cycles, released, and sampled again approximately 38 bus cycles
later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry
expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records
it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See
an example.
2.3.4
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard
output driver, and no output slew rate control.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5
The V
for the ADC module.
2.3.6
The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions.
If the IRQ function is not enabled, this pin does not perform any function.
Freescale Semiconductor
REFH
RESET Pin
Background/Mode Select (BKGD/MS)
ADC Reference Pins (V
External Interrupt Pin (IRQ)
and V
REFL
pins are the voltage reference high and voltage reference low inputs respectively
MC9S08AW60 Data Sheet, Rev 2
REFH
, V
REFL
)
Chapter 2 Pins and Connections
Figure 2-4
for
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