MC9S08AW16MFGE Freescale Semiconductor, MC9S08AW16MFGE Datasheet - Page 66

• Manufacturer Part Number: MC9S08AW16MFGE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW16MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Chapter 5 Resets, Interrupts, and System Configuration
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module
switches to self-clocked mode with the frequency of f
bus cycles where the internal bus frequency is half the ICG frequency. After the 34 bus cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 bus cycles to determine whether the reset
pin is the cause of the MCU reset.
5.4
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point. The COP
watchdog is enabled by the COPE bit in SOPT (see
additional information). The COP timer is reset by writing any value to the address of SRS. This write does
not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a
reset signal to the COP timer.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing
as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE
bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods
(2
and COPT, the user should write to write-once SOPT during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost.
The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
When the MCU is in active background mode, the COP timer is temporarily disabled.
5.5
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The
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18
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•
•
•
or 2
Illegal opcode detect
Background debug forced reset
The reset pin (RESET)
Clock generator loss of lock and loss of clock reset
13
Computer Operating Properly (COP) Watchdog
Interrupts
cycles of the bus rate clock). Even if the application will use the reset default settings in COPE
MC9S08AW60 Data Sheet, Rev 2
Section 5.9.4, “System Options Register
Self_reset
selected. The reset pin is driven low for 34
Freescale Semiconductor
(SOPT)” for