MC9S08AW16MFGE Freescale Semiconductor, MC9S08AW16MFGE Datasheet - Page 91

• Manufacturer Part Number: MC9S08AW16MFGE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW16MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.3
Port B parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTBDD[7:0]
PTBD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTBDD7
PTBD7
Port B I/O Registers (PTBD and PTBDD)
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
0
0
7
7
PTBDD6
PTBD6
0
0
6
6
Figure 6-15. Data Direction for Port B (PTBDD)
Table 6-8. PTBDD Register Field Descriptions
Table 6-7. PTBD Register Field Descriptions
Figure 6-14. Port B Data Register (PTBD)
PTBDD5
PTBD5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTBDD4
PTBD4
0
0
4
4
Description
Description
PTBDD3
PTBD3
3
0
3
0
PTBDD2
PTBD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTBDD1
PTBD1
0
0
1
1
PTBDD0
PTBD0
0
0
0
0
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