DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 148
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 148 of 794
- Download datasheet (5Mb)
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x:
Rev. 5.00 Mar. 06, 2009 Page 128 of 770
REJ09B0243-0500
Bit
5, 4
3, 2
1, 0
Don't care.
Bit Name
IDB[1:0]
RWB[1:0]
SZB[1:0]
Initial
Value
00
00
0
R/W
R/W
R/W
R/W
Description
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
Read/Write Select B
Select the read cycle or write cycle as the bus cycle of
the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
Operand Size Select B
Select the operand size of the bus cycle for the
channel B break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Note:
data access cycle
When specifying the operand size, specify the
size which matches the address boundary.
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