DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 641
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 641 of 794
- Download datasheet (5Mb)
(2.11) Programming
(2.12) The return value in the programming program, FPFR (general register R0) is checked.
(2.13) Determine whether programming of the necessary data has finished.
(2.14) After programming finishes, clear FKEY and specify software protection.
MOV.L #DLTOP+16,R1
JSR
NOP
There is an entry point of the programming program in the area from (download start address
set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
⎯ The general registers other than R0 are saved in the programming program.
⎯ R0 is a return value of the FPFR parameter.
⎯ Since the stack area is used in the programming program, a stack area of maximum 128
If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-
byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by
128 bytes and update the programming data pointer correctly. If an address which has already
been programmed is written to again, not only will a programming error occur, but also flash
memory will be damaged.
If this LSI is restarted by a power-on reset immediately after user MAT programming has
finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
• FMPDR setting
bytes must be reserved in RAM.
parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0)
must be in the 128-byte boundary of H'00 or H'80.
If the storage destination of the program data is flash memory, even when the program
execution routine is executed, programming is not executed and an error is returned to
the FPFR parameter. In this case, the program data must be transferred to on-chip RAM
and then programming must be executed.
@R1
; Set entry address to R1
; Call programming routine
Rev. 5.00 Mar. 06, 2009 Page 621 of 770
REJ09B0243-0500
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