DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 549
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 549 of 794
- Download datasheet (5Mb)
Note:
• Port A Control Register L1 (PACRL1)
Initial value:
Bit
3
2
1
0
Bit
15
14
13
12
R/W:
Bit:
* E10A cannot be used on the 32 Kbyte (SH71251A and SH71241A) and 16 Kbyte
15
R
0
Bit Name
⎯
PA4MD2
PA4MD1
PA4MD0
-
Bit Name
⎯
PA3MD2
PA3MD1
PA3MD0
(SH71250A and SH71240A) versions.
R/W
MD2
PA3
14
0
R/W
MD1
PA3
13
0
Initial
Value
0
0
0
0
Initial
Value
0
0
0
0
R/W
MD0
PA3
12
0
11
R
0
-
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
MD2
PA2
10
0
R/W
MD1
PA2
9
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
PA4 Mode
Select the function of the PA4/IRQ2/TXD1/TMS pin.
When the E10A* is in use (ASEMD0 = low), function
is fixed to TCK input.
000: PA4 I/O (port)
001: TXD1 output (SCI)
111: IRQ2 input (INTC)
Other than above: Setting prohibited
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
PA3 Mode
Select the function of the PA3/IRQ1/RXD1/TRST pin.
When the E10A* is in use (ASEMD0 = low), function
is fixed to TRST input.
000: PA3 I/O (port)
001: RXD1 input (SCI)
111: IRQ1 input (INTC)
Other than above: Setting prohibited
R/W
MD0
PA2
8
0
R
7
0
-
R/W
MD2
PA1
Rev. 5.00 Mar. 06, 2009 Page 529 of 770
6
0
R/W
MD1
PA1
5
0
R/W
MD0
PA1
4
0
R
3
0
-
REJ09B0243-0500
R/W
MD2
PA0
2
0
R/W
MD1
PA0
1
0
R/W
MD0
PA0
0
0
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