DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 438
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 438 of 794
- Download datasheet (5Mb)
12.3.4
SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the
transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into
SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during
serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be
written or read to by the CPU.
12.3.5
SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR.
Rev. 5.00 Mar. 06, 2009 Page 418 of 770
REJ09B0243-0500
Bit
7
Transmit Data Register (SCTDR)
Serial Mode Register (SCSMR)
Bit Name
C/A
Initial value:
Initial value:
Initial
value
0
R/W:
R/W:
Bit:
Bit:
R/W
R/W
C/A
7
7
0
-
R/W
R/W
R/W
R/W
CHR
6
6
0
-
Description
Communication Mode
Selects whether the SCI operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode (Channel 1 in the SH7124
R/W
R/W
PE
5
5
0
-
is not available.)
R/W
R/W
O/E
4
4
0
-
STOP
R/W
R/W
3
3
0
-
R/W
R/W
MP
2
2
0
-
R/W
R/W
1
1
0
-
CKS[1:0]
R/W
R/W
0
0
0
-
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