DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 272

• Manufacturer Part Number: DF71241D50FPV
• Description: MCU RISC FLASH 5V 32K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71241D50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Cascaded Operation Example (c) in SH7125: Figure 9.23 illustrates the operation when
TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to
1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture
conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2
have selected both the rising and falling edges for the input capture timing. Under these
conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2
input capture conditions.
Cascaded Operation Example (d) in SH7125: Figure 9.24 illustrates the operation when
TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include
the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits
in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input
capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for
the input capture timing.
Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture
occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture
condition although the I2AE bit in TICCR has been set to 1.
Rev. 5.00 Mar. 06, 2009 Page 252 of 770
REJ09B0243-0500
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_2 value
Figure 9.23 Cascaded Operation Example (c)
H'0512
H'0512
H'6128
H'0513
H'2064
H'0513
H'C256
H'0514
H'0514
H'9192
Time