DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 256
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 256 of 794
- Download datasheet (5Mb)
Note:
9.3.31
The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle
buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR),
timer A/D converter start request control register (TADCR), timer A/D converter start request
cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers
(TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-
bit read/write is not possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. These are connected to the CPU by a
16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
Rev. 5.00 Mar. 06, 2009 Page 236 of 770
REJ09B0243-0500
Bit
0
* Do not set to 1 when complementary PWM mode is not selected.
Bit Name
WRE
Bus Master Interface
Initial
Value
0
R/W
R/(W)
Description
Selects the waveform output when synchronous
counter clearing occurs in complementary PWM mode.
The output waveform is retained only when
synchronous clearing occurs within the Tb interval at
the trough in complementary PWM mode. When
synchronous clearing occurs outside this interval, the
initial value specified in TOCR is output regardless of
the WRE bit setting. The initial value is also output
when synchronous clearing occurs in the Tb interval at
the trough immediately after TCNT_3 and TCNT_4 start
operation.
For the Tb interval at the trough in complementary
PWM mode, see figure 9.40.
0: Outputs the initial value specified in TOCR
1: Retains the waveform output immediately before
[Setting condition]
•
Waveform Retain Enable
synchronous clearing
When 1 is written to WRE after reading WRE = 0
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