DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 606

• Manufacturer Part Number: DF71241D50FPV
• Description: MCU RISC FLASH 5V 32K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71241D50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Download of On-Chip Program
(3) Initialization of Programming/Erasing
(4) Programming/Erasing Execution
(5) When Programming/Erasing is Executed Consecutively
Rev. 5.00 Mar. 06, 2009 Page 586 of 770
REJ09B0243-0500
The on-chip program is automatically downloaded by clearing VBR of the CPU to
H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS)
and the flash key code register (FKEY), which are programming/erasing interface registers.
The user MAT is replaced to the embedded program storage area when downloading. Since the
flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in a space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameters,
whether the normal download is executed or not can be confirmed.
Note that VBR can be changed after download is completed.
The operating frequency and user branch are set before execution of programming/erasing.
The user branch destination must be in an area other than the user MAT area, which is in the
middle of programming and the area where the on-chip program is downloaded. These settings
are performed by using the programming/erasing interface parameters.
To program or erase, the FWE pin must be brought high and user program mode must be
entered.
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameters and the on-
chip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction to perform the subroutine call of the specified address in the on-chip RAM. The
execution result is returned to the programming/erasing interface parameters.
The area to be programmed must be erased in advance when programming flash memory.
There are limitations and notes on the interrupt processing during programming/erasing. For
details, see section 17.7.1, Interrupts during Programming/Erasing.
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.