DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 60
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 60 of 794
- Download datasheet (5Mb)
Note:
Rev. 5.00 Mar. 06, 2009 Page 40 of 770
REJ09B0243-0500
Instruction
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
* Indicates the number of execution cycles for normal operation.
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+
@Rm+,@Rn+
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Operation
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Rn - 1 → Rn, if Rn = 0, 1 →
T, else 0 → T
A byte in Rm is sign-
extended → Rn
A word in Rm is sign-
extended → Rn
A byte in Rm is zero-
extended → Rn
A word in Rm is zero-
extended → Rn
Signed operation of (Rn)
× (Rm) + MAC → MAC,
32 × 32 + 64 → 64 bits
Signed operation of (Rn)
× (Rm) + MAC → MAC,
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed operation of Rn
× Rm → MAC
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bits
0-Rm → Rn
0-Rm-T → Rn,
Borrow → T
Rn-Rm → Rn
Rn-Rm–T → Rn,
Borrow → T
Rn-Rm → Rn,
Underflow → T
Code
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Execution
Cycles
2 to 5*
1
1
1
1
1
2 to 5*
2 to 4*
2 to 5*
1 to 3*
1 to 3*
1
1
1
1
1
T Bit
⎯
Comparison
result
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Borrow
⎯
Borrow
Underflow
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