DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 155
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 155 of 794
- Download datasheet (5Mb)
7.2.14
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 by a power-on reset or manual reset when BRDR is read or the setting to enable PC
trace is made. Other bits are not initialized by a power-on reset. The eight BRDR registers have a
queue structure and a stored register is shifted at every branch.
Initial value:
Initial value:
Bit
31
30 to 28 ⎯
27 to 0
R/W:
R/W:
Bit:
Bit:
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9
Branch Destination Register (BRDR)
DVF
31
15
R
R
Bit Name
DVF
BDA27 to
BDA0
0
-
30
14
R
R
0
-
-
29
13
R
R
0
-
-
Initial
Value
0
All 0
Undefined R
28
12
R
R
0
-
-
BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
27
11
R
R
-
-
R/W
R
R
26
10
R
R
-
-
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. This flag bit is set to 1 when a branch occurs.
This flag is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
Reserved
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
These bits are always read as 0. The write value
should always be 0.
25
R
R
9
-
-
BDA8
24
R
R
8
-
-
BDA7
23
R
R
7
-
-
BDA6
22
R
R
Rev. 5.00 Mar. 06, 2009 Page 135 of 770
6
-
-
BDA5
21
R
R
5
-
-
BDA4
20
R
R
4
-
-
BDA3
19
R
R
3
-
-
REJ09B0243-0500
BDA2
18
R
R
2
-
-
BDA1
17
R
R
1
-
-
BDA0
16
R
R
0
-
-
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