COP8CCE9IMT7/NOPB National Semiconductor, COP8CCE9IMT7/NOPB Datasheet - Page 12

• Manufacturer Part Number: COP8CCE9IMT7/NOPB
• Description: MCU 8BIT FLASH 8K MEM 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8CCE9IMT7

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AC Electrical Characteristics (0˚C ≤ T
Resolution
DNL
DNL
INL
INL
Offset Error
Offset Error
Gain Error
Gain Error
Input Voltage Range
Analog Input Leakage Current
Analog Input Resistance (Note 11)
Analog Input Capacitance
MICROWIRE/PLUS Output Propagation
Delay (t
Input Pulse Width
Output Pulse Width
USART Bit Time when using External
CKX
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
Reset Pulse Width
t
Note 2: Maximum rate of voltage change must be
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of I
H and L programmed as low outputs and not driving a load; all inputs tied to V
mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
biased at voltages
be limited to
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: V
Note 9: Corresponds to 10 MHz maximum input clock frequency.
Note 10: Corresponds to 3.33 MHz maximum input clock frequency.
A/D Converter Electrical Characteristics (0˚C ≤ T
mode only)
C
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2 Input High Time (Note 6)
Timer 2 Input Low Time (Note 6)
Timer 2 Output High Time
Timer 2 Output Low Time
= instruction cycle time.
UPD
cc
must be valid and stable before G6 is raised to a high voltage.
<
)
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
>
Parameter
Parameter
V
CC
(the pins do not have source current when biased at a voltage below V
<
0.5 V/ms.
V
V
V
V
V
V
V
V
2.7V ≤ V
CC
CC
CC
CC
CC
CC
CC
CC
= 5V
= 3V
= 5V
= 3V
= 5V
= 3V
= 5V
= 3V
Conditions
Conditions
CC
DD
<
HALT is done with device neither sourcing nor sinking current; with A. B, G0, G2–G5,
5.5V
CC
12
A
; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT
≤ +70˚C)
Min
0
CC
). These two pins will not latch up. The voltage at the pins must
periods
6 CKI
Min
150
150
1
1
1
1
1
1
1
(Continued)
A
>
≤ +70˚C) (Single-ended
Typ
V
CC
and the pins will have sink current to V
Typ
+1.5/− 3.5
+0.5/− 2.0
+0.5/− 4.5
Max
±
V
0.5
10
±
±
±
±
6k
C
1.5
7
CC
1
1
3
5
.
Max
150
2
MCLK or
MCLK or
Units
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MHz
Bits
µA
pF
CC
ns
ns
ns
V
Ω
t
t
t
t
t
t
t
C
C
C
C
C
C
C
when
CC