COP8CCE9IMT7/NOPB National Semiconductor, COP8CCE9IMT7/NOPB Datasheet - Page 71

• Manufacturer Part Number: COP8CCE9IMT7/NOPB
• Description: MCU 8BIT FLASH 8K MEM 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8CCE9IMT7

20.0 Instruction Set
20.7 INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
JSRL
JSR
JSRB
JID
RET
RETSK
RETI
INTR
NOP
Addr.
Addr.
Addr
RPND
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Jump SubRoutine Long
Jump SubRoutine
Jump SubRoutine Boot ROM
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
Direct
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
(Continued)
1/1
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
71
Instructions Using A & C
Transfer of Control Instructions
[SP] ← PL, [SP−1] ← PU,SP−2, PC ← ii
[SP] ← PL, [SP−1] ← PU,SP−2, PC9…0 ← i
[SP] ← PL, [SP−1] ← PU,SP−2,
PL ← Addr,PU ← 00, switch to flash
PL ← ROM (PU,A)
SP + 2, PL ← [SP], PU ← [SP−1]
SP + 2, PL ← [SP],PU ← [SP−1],
skip next instruction
SP + 2, PL ← [SP],PU ← [SP−1],GIE ← 1
[SP] ← PL, [SP−1] ← PU, SP−2, PC ← 0FF
PC ← PC + 1
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
JMPL
JMP
JP
JSRL
JSR
JSRB
JID
VIS
RET
RETSK
RETI
INTR
NOP
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
3/4
2/3
1/3
3/5
2/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
www.national.com