MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 110

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Memory
4.5.2
The instruction cache is physically connected to the ColdFire core's local bus, allowing it to service all
instruction fetches from the ColdFire core and certain memory fetches initiated by the debug module.
Typically, the debug module's memory references appear as supervisor data accesses but the unit can be
programmed to generate user-mode accesses and/or instruction fetches. The instruction cache processes
any instruction fetch access in the normal manner.
4.5.2.1
Because both the instruction cache and high-speed SRAM module are connected to the ColdFire core's
local data bus, certain user-defined configurations can result in simultaneous instruction fetch processing.
If the referenced address is mapped into the SRAM module, that module services the request in a single
cycle. In this case, data accessed from the instruction cache is discarded without generating external
memory references. If the address is not mapped into SRAM space, the instruction cache handles the
request in the normal fashion.
4.5.2.2
The instruction cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain cache coherency by invalidating the appropriate cache entries after
modifying code segments.
4-8
31
Instruction Cache Operation
Local Address Bus
Interaction with Other Modules
Cache Coherency and Invalidation
MCF5272 ColdFire
9
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Figure 4-3. Instruction Cache Block Diagram
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External Data[31:0]
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MUX
Local Data Bus
Data
MUX
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