MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 328

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Physical Layer Interface Controller (PLIC)
13.5.20 D-Channel Request Register (PDRQR)
All bits in this read/write register are cleared on hardware or software reset.
The PDRQR register contains D-channel control bits for all four ports on the MCF5272.
13-32
15–12
11, 9
10, 8
Bits
7–2
1–0
Reset
Field
Addr
R/W
15
DCNTI
SHDD
Name
DRQ
—
—
—
MCF5272 ColdFire
Reserved, should be cleared.
D-channel shift direction.
0 D-channel data is msb first. The first bit received is assumed to be the most significant bit and is
1 D-channel data is lsb first for the D channel. The first bit received is assumed to be the least
D-channel control ignore. Allows the D-Channel contention function to be ignored.
Reserved, should be cleared.
The value written to these bits is driven onto the DREQ pins associated with port 0 and port 1. When
set, a logic high, 1, is driven on to the corresponding pin.
12
loaded into the msb position of the D-channel receive register for the respective port. SHDD(1)
configures the shift direction for ports 1, 2 and 3, SHDD(0) configures the shift direction for port 0.
significant bit and is loaded into the lsb position of the D-channel receive register for the
respective port.
00 contention active on both ports
01 ignore contention on port 0
10 ignore contention on port 1
11 ignore contention on both ports
Figure 13-32. D-Channel Request Registers (PDRQR)
SHDD(1) DCNTI(1) SHDD(0) DCNTI(0)
11
Table 13-15. PDRQR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
10
0000_0000_0000_0000
MBAR + 0x392
9
Read/Write
Description
8
7
—
2
Freescale Semiconductor
1
DRQ
0