MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 279

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
1
0
IN_DONE
STALL
Name
MCF5272 ColdFire
This bit controls the USB's response to IN tokens from the host. Set at Reset and on an EOT event
and must be cleared by software when the last byte of a transfer has been written to the IN-FIFO. This
bit is then subsequently set by the USB core when an end of transfer (EOT) event occurs, indicating
that the transfer has been completed. An end of transfer (EOT) event is indicated by one of the
following:
a) An IN packet is transmitted that contains less than the maximum number of bytes defined at
b) A zero length IN packet is transmitted. This occurs when the previously transmitted IN packet was
0 CPU has completed writing to the IN-FIFO and transfer is in progress. The USB module sends all
1 Transfer completed or CPU is busy writing to the IN-FIFO. The USB module only sends
Force STALL response. Causes the endpoint to return a STALL handshake when polled by either IN
or OUT token by the USB host controller. The STALL handshake causes the endpoint to be halted.
The STALL bit is not valid for isochronous endpoints. This command bit is write-only and always
returns 0 when read.
0 Default
1 Send STALL handshake
the data in the FIFO, or a zero-length packet when the FIFO is empty.
maximum-sized packets or NAK responses if the FIFO contains less data than the maximum
packet size.
endpoint configuration.
full, and no more data remains in the IN-FIFO. Hence a single zero length packet must be sent to
indicate EOT.
Table 12-13. EP
®
Integrated Microprocessor User’s Manual, Rev. 3
n
CTL Field Descriptions
Description
Universal Serial Bus (USB)
12-21