MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 19

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
11.5 Programming Model ................................................................................................................ 11-10
11.6 Buffer Descriptors .................................................................................................................... 11-34
11.7 Differences between MCF5272 FEC and MPC860T FEC ...................................................... 11-39
Freescale Semiconductor
11.4.5 Interpacket Gap Time ..................................................................................................... 11-8
11.4.6 Collision Handling .......................................................................................................... 11-8
11.4.7 Internal and External Loopback ..................................................................................... 11-8
11.4.8 Ethernet Error-Handling Procedure ................................................................................ 11-9
11.5.1 Ethernet Control Register (ECR) ...................................................................................11-11
11.5.2 Interrupt Event Register (EIR) ..................................................................................... 11-12
11.5.3 Interrupt Mask Register (EIMR) .................................................................................. 11-13
11.5.4 Interrupt Vector Status Register (IVSR) ....................................................................... 11-14
11.5.5 Receive Descriptor Active Register (RDAR) ............................................................... 11-15
11.5.6 Transmit Descriptor Active Register (TDAR) ............................................................. 11-16
11.5.7 MII Management Frame Register (MMFR) ................................................................. 11-17
11.5.8 MII Speed Control Register (MSCR) ........................................................................... 11-18
11.5.9 FIFO Receive Bound Register (FRBR) ........................................................................ 11-19
11.5.10 FIFO Receive Start Register (FRSR) ......................................................................... 11-20
11.5.11 Transmit FIFO Watermark (TFWR) ........................................................................... 11-21
11.5.12 FIFO Transmit Start Register (TFSR) ........................................................................ 11-22
11.5.13 Receive Control Register (RCR) ................................................................................ 11-23
11.5.14 Maximum Frame Length Register (MFLR) ............................................................... 11-24
11.5.15 Transmit Control Register (TCR) ............................................................................... 11-25
11.5.16 RAM Perfect Match Address Low (MALR) .............................................................. 11-26
11.5.17 Hash Table High (HTUR) ........................................................................................... 11-28
11.5.18 Hash Table Low (HTLR) ............................................................................................ 11-29
11.5.19 Pointer-to-Receive Descriptor Ring (ERDSR) ........................................................... 11-30
11.5.20 Pointer-to-Transmit Descriptor Ring (ETDSR) .......................................................... 11-31
11.5.21 Receive Buffer Size Register (EMRBR) .................................................................... 11-32
11.5.22 Initialization Sequence ............................................................................................... 11-33
11.5.23 User Initialization (Prior to Asserting ETHER_EN) .................................................. 11-33
11.5.24 FEC Initialization ....................................................................................................... 11-34
11.6.1 FEC Buffer Descriptor Tables ...................................................................................... 11-35
11.4.8.1 Transmission Errors .......................................................................................... 11-9
11.4.8.2 Reception Errors ............................................................................................... 11-9
11.5.16.1 RAM Perfect Match Address High (MAUR) ............................................... 11-27
11.5.22.1 Hardware Initialization ................................................................................. 11-33
11.5.24.1 User Initialization (after setting ETHER_EN) .............................................. 11-34
11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) .................................................. 11-35
11.6.1.2 Ethernet Transmit Buffer Descriptor .............................................................. 11-37
MCF5272 ColdFire
Table of Contents (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
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