MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 181

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.2.4
The programmable interrupt transition register (PITR),
high-to-low or low-to-high) on each of the external interrupt inputs.
Table 7-5
Freescale Semiconductor
31–28,
27–7,
Bits
6, 5
4–0
Reset
Reset
Field INT1 INT2 INT3 INT4
Field
Addr
R/W
describes PITR fields.
Name
Programmable Interrupt Transition Register (PITR)
—
—
31
15
30
0 Triggering edge of external interrupt input is high-to-low (negative edge triggered).
1 Triggering edge of external interrupt input is low -to-high (positive edge triggered).
Reserved, should be cleared.
Figure 7-7. Programmable Interrupt Transition Register (PITR)
MCF5272 ColdFire
29
28
27
—
Table 7-5. PITR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x034
R/W
Figure
7
Description
INT5
7-7, specifies the triggering (either
6
—
INT6
5
4
—
Interrupt Controller
16
0
7-7