MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 5
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MCF5272VM66J
Manufacturer:
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Quantity:
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MCF5272VM66J
Manufacturer:
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MCF5272VM66J
Manufacturer:
Freescale Semiconductor
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Freescale Semiconductor
MCF5272 Block Diagram ........................................................................................................ 1-2
ColdFire Pipeline..................................................................................................................... 2-2
ColdFire Multiply-Accumulate Functionality Diagram.............................................................. 2-3
ColdFire Programming Model ................................................................................................. 2-5
Condition Code Register (CCR).............................................................................................. 2-6
Status Register (SR) ............................................................................................................... 2-8
Vector Base Register (VBR) ................................................................................................... 2-8
Organization of Integer Data Formats in Data Registers ...................................................... 2-10
Organization of Integer Data Formats in Address Registers................................................. 2-10
Memory Operand Addressing ............................................................................................... 2-11
Exception Stack Frame Form................................................................................................ 2-27
ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1
MAC Programming Model....................................................................................................... 3-2
SRAM Base Address Register (RAMBAR) ............................................................................. 4-3
Instruction Cache Block Diagram............................................................................................ 4-8
Cache Control Register (CACR) ........................................................................................... 4-12
Access Control Register Format (ACRn) .............................................................................. 4-14
Processor/Debug Module Interface......................................................................................... 5-1
PSTCLK Timing ...................................................................................................................... 5-2
Example JMP Instruction Output on PST/DDATA .................................................................. 5-5
Debug Programming Model .................................................................................................... 5-6
Address Attribute Trigger Register (AATR)............................................................................. 5-7
Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9
Configuration/Status Register (CSR) .................................................................................... 5-10
Data Breakpoint/Mask Registers (DBR and DBMR) ............................................................. 5-12
Program Counter Breakpoint Register (PBR) ....................................................................... 5-13
Program Counter Breakpoint Mask Register (PBMR)........................................................... 5-13
Trigger Definition Register (TDR).......................................................................................... 5-14
BDM Serial Interface Timing ................................................................................................. 5-17
Receive BDM Packet ............................................................................................................ 5-18
Transmit BDM Packet ........................................................................................................... 5-18
BDM Command Format ........................................................................................................ 5-20
Command Sequence Diagram.............................................................................................. 5-21
RAREG
RAREG
WAREG
WAREG
READ
READ
ROM Base Address Register (ROMBAR).............................................................................. 4-5
Command/Result Formats ........................................................................................... 5-24
Command Sequence ................................................................................................... 5-24
/
/
/
/
RDREG
RDREG
WDREG
WDREG
MCF5272 ColdFire
Command Format .......................................................................................... 5-22
Command Sequence...................................................................................... 5-22
Command Format ......................................................................................... 5-23
Command Sequence .................................................................................... 5-23
®
List of Figures
Integrated Microprocessor User’s Manual, Rev. 3
Title
Number
Page
v
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