MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 42
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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This manual includes the following two appendixes:
This manual also includes an index.
xlii
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Chapter 17, “General Purpose I/O
the three general purpose I/O (GPIO) ports on the MCF5272. The chapter details pin assignment,
direction-control, and data registers.
Chapter 18, “Pulse-Width Modulation (PWM)
of the pulse-width modulation (PWM) module. It includes a block diagram, programming model,
and timing diagram.
Chapter 19, “Signal
signals. Specifically, it shows which are inputs or outputs, how they are multiplexed, and the state
of each signal at reset. The first listing is organized by function, with signals appearing
alphabetically within each functional group. This is followed by a second listing sorted by pin
number.
Chapter 20, “Bus
error conditions, bus arbitration, and reset operations. It includes detailed timing diagrams showing
signal interaction. Operation of the bus is defined for transfers initiated by the MCF5272 as a bus
master. The MCF5272 does not support external bus masters. Note that
Controller,” describes DRAM cycles.
Chapter 21, “IEEE 1149.1 Test Access Port
MCF5272 Joint Test Action Group (JTAG) implementation. It describes those items required by
the IEEE 1149.1 standard and provides additional information specific to the MCF5272. For
internal details and sample applications, see the IEEE 1149.1 document.
Chapter 22, “Mechanical
MCF5272.
Chapter 23, “Electrical
thermal characteristics for the MCF5272. Because additional speeds may have become available
since the publication of this book, consult Freescale’s ColdFire web page,
http://www.freescale.com, to confirm that this is the latest information.
Appendix A, “List of Memory
memory-mapped registers.
Appendix B, “Buffering and Impedance
interface circuitry between the MCF5272 and SDRAMs.
MCF5272 ColdFire
Operation,” describes the functioning of the bus for data-transfer operations,
Descriptions,” provides a listing and brief description of all the MCF5272
Characteristics,” describes AC and DC electrical specifications and
Data,” provides a functional pin listing and package diagram for the
®
Maps,” provides the entire address-map for MCF5272
Integrated Microprocessor User’s Manual, Rev. 3
Module,” describes the operation and programming model of
Matching,” provides some suggestions regarding
(JTAG),” describes configuration and operation of the
Module,” describes the configuration and operation
Chapter 9, “SDRAM
Freescale Semiconductor
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