DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 12

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
9.8.5 Chain Transfer
10.1.4 Pin Functions
• P10/PO8/TIOCA0
10.9.7 Pin Functions
• PA7/A23/IRQ7,
• PA4/A20/IRQ4
• PA3/A19, PA2/A18,
10.10.5 Pin Functions
10.11.5 Pin Functions
Rev.7.00 Mar. 18, 2009 page x of lxvi
REJ09B0109-0700
PA6/A22/IRQ6,
PA5/A21/IRQ5
PA1/A17, PA20/A16
Page
453
471
511
511
512
515
519
Revision (See Manual for Details)
Description amended
… SCI and
the other hand, are cleared when the DTC reads or writes to the
prescribed register.
Table amended
Table amended
Table amended
Table amended
Table amended
Legend added
Legend: n = 7 to 0
Table amended
TPU channel 0
settings
Pin function
Pin
function
Operating
mode
Pin
function
Pin
function
PBnDDR
Pin function
PCnDDR
Pin function
Address
Address
output
output
input
PAn
1, 2
Address
Address
output
output
—
—
TIOCA0 output
input
input
output
PAn
PA4
PAn
(1) in table
below
A/D converter interrupt/activation sources, on
output
output
PA4
PAn
input
input
PBn
PCn
input
PAn
0
0
4
input
input
PA4
PAn
Address
output
Address
Address
output
output
P10 input
1
1
Address
Address
output
IRQn interrupt input *
output
IRQ4 interrupt input *
input
PAn
input
input
PBn
PCn
input
PA4
input
PAn
0
0
output
PAn
(2) in table below
TIOCA0 input *
output
output
PA4
PAn
P10 output
output
output
PBn
PCn
1
1
input
input
input
PA4
PAn
1
7
output
input
input
PBn
PCn
PAn
output
output
0
0
PAn
PA4
PO8 output
input
PAn
input
input
Address
Address
PAn
PA4
output
output
1
1
Address
Address
Address
output
output
output