DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 258
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller (BSC)
Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
Rev.7.00 Mar. 18, 2009 page 190 of 1136
REJ09B0109-0700
Read
(when
RDNn = 0)
Write
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended
φ
Address bus
CSn
AS
RD
Data bus
HWR, LWR
Data bus
t
h
state with the lower 8 bits (CSXT7 to CSXT0).
inserted before the basic bus cycle and extension state T
h
T
state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
h
T
1
Bus cycle
T
Write data
2
Read data
T
3
t
inserted after the
T
t
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