DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 185
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.9
This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration).
There are two bus mastersthe CPU and DMACthat perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.9.1
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus master is as follows:
6.9.2
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
• If the CPU is in sleep mode, the bus is transferred immediately.
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
(High) DMAC > CPU (Low)
Bus Arbitration
Operation
Bus Transfer Timing
Rev. 2.00, 03/04, page 151 of 534
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