DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 444

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

8. The return value in the initialization program, FPFR (general register R0L) is determined.
9. All interrupts and the use of a bus master (DMAC) other than the CPU are prohibited.
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
Rev. 2.00, 03/04, page 410 of 534
 The general registers other than R0L are held in the initialization program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the initialization program, 128-byte stack area at the
 Interrupts can be accepted during the execution of the initialization program. The program
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, the
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts and bus mastership to the DMAC are prohibited.
To prohibit the interrupt, bit 7 (I) in the condition code register (CCR) of the CPU should be
set to B'1 in interrupt control mode 0 or bits 2 to 0 (I2 to I0) in the extend control register of
the CPU should be set to B′111 in interrupt control mode 2. Then interrupts other than NMI
are held and are not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to the DMAC, the error protection state is entered.
Therefore, taking bus mastership by the DMAC is prohibited.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
 Example of the FMPAR setting
maximum must be allocated in RAM.
storage area and stack area in the on-chip RAM and register values must not be destroyed.
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits of the address must be H'00 or H'80 as the
boundary of 128 bytes.