DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 227

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared, and DREQ pin high level sampling for edge sensing is started. If DREQ pin high level
sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the
write cycle, and DREQ pin low level sampling is performed again; this sequence of operations is
repeated until the end of the transfer.
DREQ Pin Low Level Activation Timing: Figure 7.22 shows an example of normal mode
transfer activated by the DREQ pin low level.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle start;
[4], [7] When
φ
Address bus
DMA control
Channel
Acceptance after transfer enabling;
(As in [1],
Idle
Figure 7.21 Example of Block Transfer Mode Transfer Activated
[1]
Minimum 3 cycles
Bus release
Request
pin high level has been sampled, acceptance is resumed after completion of dead cycle.
pin low level is sampled at rise of φ, and request is held.)
[2]
pin high level sampling is started at rise of φ.
Read
Request clearance period
[3]
Transfer source
DMA read
by DREQ Pin Falling Edge
One block transfer
Write
DMA write
destination
pin low level is sampled at rise of φ, and request is held.
Transfer
Acceptance
resumed
Idle
[4]
Minimum 3 cycles
Request
Bus release
[5]
Rev. 2.00, 03/04, page 193 of 534
Request clearance period
Read
[6]
Transfer source
DMA read
One block transfer
Write
DMA write Bus release
destination
Transfer
Acceptance
resumed
Idle
[7]