DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 443
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
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Part Number:
DF2170VTE33V
Manufacturer:
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Quantity:
10 000
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4. FKEY is cleared to H'00 for protection.
5. The value of the DPFR parameter must be checked and the download result must be
6. The operating frequency and user branch destination are set to the FPEFEQ and FUBRA
7. Initialization
When hardware standby mode is entered during download processing, the normal
Since a stack area of 128 bytes at the maximum is used, the area must be allocated before
If a flash memory access by the DMAC signal is requested during downloading, the
confirmed.
Check the value of the DPFR parameter (one byte of start address of the download
If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
If the value of the DPFR parameter is different from before downloading, check the SS bit
parameters for initialization.
The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the start
address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and
initialization is executed by using the following steps.
MOV.L
JSR
NOP
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
setting the SCO bit to 1.
operation cannot be guaranteed. Therefore, an access request by the DMAC signal must not
be generated.
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
ER0).
The settable range of the FPEFEQ parameter is 5 to 33 MHz. When the frequency is set to
out of this range, an error is returned to the FPFR parameter of the initialization program
and initialization is not performed. For details on the frequency setting, see the description
in 14.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ).
#DLTOP+32,ER2
@ER2
; Set entry address to ER2
; Call initialization routine
Rev. 2.00, 03/04, page 409 of 534
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