DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 43

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

Type
Interrupt
signals
Address bus A19
Data bus
Bus control
Symbol
NMI
IRQ7 to
IRQ0
(IRQ7) to
(IRQ0)
A18
A17
A16
A15 to A8
A7 to A0
D15 to D8,
D7 to D0
CS3
CS2/
RAS
CS1
CS0
AS
RD
HWR
LWR
UCAS
LCAS
Pin No.
6
71 to 78
91, 92,
28, 27,
95, 96,
99, 100
2,
1,
100,
99,
59 to 66,
71 to 78
79 to 86,
91 to 98
2
20
21
22
16
17
18
19
1
100
I/O
Input
Input
Input
Output These pins output an address.
Input/
output
Output Strobe signal indicating that area 3 is selected.
Output Strobe signal indicating that area 2 is selected. Row
Output Strobe signal indicating that area 1 is selected.
Output Strobe signal indicating that area 0 is selected.
Output When this pin is low, it indicates that address output
Output When this pin is low, it indicates that the normal
Output Strobe signal indicating that normal space is to be
Output Strobe signal indicating that normal space is to be
Output Upper column address strobe signal for accessing
Output Lower column address strobe signal for accessing
Nonmaskable interrupt request pin. Fix high when
Function
not used.
These pins request a maskable interrupt. The IRQ
sense port select register (ISSR) selects whether
the signal is input from the IRQn or (IRQn).
(n = 7 to 0)
These pins constitute a bidirectional data bus.
address strobe signal for the DRAM.
on the address bus is valid.
space is being read.
written, and the upper half (D15 to D8) of the data
bus is enabled.
written, and the lower half (D7 to D0) of the data bus
is enabled.
the 16-bit DRAM space or column address strobe
signal for accessing the 8-bit DRAM space.
the 16-bit DRAM space.
Rev. 2.00, 03/04, page 9 of 534