DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 423
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the on-chip RAM address where an on-chip program is downloaded. This
register must be specified before setting the SCO bit in FCCS to 1.
Bit
7
6
5
4
3
2
1
0
Bit
Name
TDER
TDA6
TDA5
TDA4
TDA3
TDA2
TDA1
TDA0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transfer Destination Address Setting Error
This bit is set to 1 when the address specified by bits
TDA6 to TDA0, which is the start address where an on-
chip program is downloaded, is over the range. Whether
or not the address specified by bits TDA6 to TDA0 is
within the range of H'00 to H'03 is determined when an
on-chip program is downloaded by setting the SCO bit in
FCCS to 1. Make sure that this bit is cleared to 0 and
the value specified by bits TDA6 to TDA0 is within the
range of H'00 to H'03 before setting the SCO bit to 1.
0: The value specified by bits TDA6 to TDA0 is within
1: The value specified by bits TDA6 to TDA0 is over the
Transfer Destination Address
Specifies the start address where an on-chip program is
downloaded. A value from H'00 to H'03 can be specified
as the download start address in the on-chip RAM.
H'00: H'FF7000 is specified as the download start
H'01: H'FFB000 is specified as the download start
H'02: H'FFD000 is specified as the download start
H'03: H'FFE800 is specified as the download start
H'04 to H'FF: Setting prohibited. Specifying this value
the range.
range (H'04 to H'FF) and download is stopped.
address.
address.
address.
address.
sets the TDRE bit to 1 during downloading
and stops the download.
Rev. 2.00, 03/04, page 389 of 534
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