DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 293
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.10.3
PORTA shows the pin states of the port A. PORTA cannot be modified.
Notes: 1. Determined by the state of the HUDIDI/RxD0 pin.
8.10.4
Port A pins also function as the pins for external address bus output, external bus control signal
output, and interrupt input. The correspondence between the register specification and the pin
functions is shown below.
• PA3/A19/CS3
Bit
7
6 to 4
3
2
1
0
EXPE
CS3E
AHOE
PA3DDR
Pin function
The pin function is switched as shown below according to the combination of the PA3DDR
bit, the EXPE bit in MDCR, and the CS3E and AHOE bits in PFCR1.
2. Determined by the states of pins PA3 to PA0.
Bit Name
RxDMON
PA3
PA2
PA1
PA0
Port A Register (PORTA)
Pin Functions
PA3 input
0
Initial
Value
*
Undefined
*
*
*
*
1
2
2
2
2
0
PA3 output
R/W
R
R
R
R
R
1
Description
This bit is read as the reversed value of the
HUDIDI/RxD0 pin. 1 is read when the HUDIDI/RxD0 pin
is low, and 0 is read when HUDIDI/RxD0 pin is high.
Reserved
If these bits are read, an undefined value will be read.
If a PORTA read is performed while PADDR bits are set
to 1, the PADR values are read. If a PORTA read is
performed while PADDR bits are cleared to 0, the pin
states are read.
PA3 input
0
0
PA3 output
0
1
Rev. 2.00, 03/04, page 259 of 534
1
A19 output CS3 output
1
1
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