UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 394

• Manufacturer Part Number: UPD78F9234MC-5A4-A
• Description: MCU 8BIT 8KB FLASH 30PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9234MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

392
16-bit
timer/event
counter 00
Function
CR000: 16-bit
timer capture/
compare register
000
CR010: 16-bit
timer capture/
compare register
010
TMC00: 16-bit
timer mode
control register
00
Details of
Function
If the register read period and the input of the capture trigger conflict when
CR000 is used as a capture register, the capture trigger input takes
precedence and the read data is undefined. Also, if the count stop of the timer
and the input of the capture trigger conflict, the capture trigger is undefined.
Changing the CR000 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
In the free-running mode and in the clear & start mode using the valid edge of
the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is
generated when CR010 changes from 0000H to 0001H following overflow
(FFFFH).
If the new value of CR010 is less than the value of 16-bit timer counter 0
(TM00), TM00 continues counting, overflows, and then starts counting from 0
again. If the new value of CR010 is less than the old value, therefore, the
timer must be reset to be restarted after the value of CR010 is changed.
The value of CR010 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR010 set in compare mode
even if a capture trigger is input.
If the register read period and the input of the capture trigger conflict when
CR010 is used as a capture register, the capture trigger input takes
precedence and the read data is undefined. Also, if the timer count stop and
the input of the capture trigger conflict, the capture data is undefined.
Changing the CR010 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and
TMC003 (operation stop mode) are set to a value other than 0, 0, respectively.
Set TMC002 and TMC003 to 0, 0 to stop the operation.
The timer operation must be stopped before writing to bits other than the
OVF00 flag.
If the timer is stopped, timer counts and timer interrupts do not occur, even if a
signal is input to the TI000/TI010 pins.
Except when the valid edge of the TI000 pin is selected as the count clock,
stop the timer operation before setting STOP mode or system clock stop
mode; otherwise the timer may malfunction when the system clock starts.
Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register
00 (PRM00) after stopping the timer operation.
If the clear & start mode entered on a match between TM00 and CR000, clear
& start mode at the valid edge of the TI000 pin, or free-running mode is
selected, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
Even if the OVF00 flag is cleared before the next count clock is counted
(before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the
OVF00 flag is re-set newly and clear is disabled.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17446EJ5V0UD
Cautions
pp.
91, 125
p.92
pp.
92, 122
pp.
92, 122
pp.
pp.
pp.
p.93
pp.
93, 122
pp.
pp.
pp.
pp.
p.94
92, 123
92, 126
93, 125
94, 123
94, 122
94, 127
94, 123
pp.
94, 124
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