UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 405

• Manufacturer Part Number: UPD78F9234MC-5A4-A
• Description: MCU 8BIT 8KB FLASH 30PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9234MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt
function
Standby
function
Function
Vector table
address
IF0, IF1: Interrupt
request flag
registers 0, 1
MK0, MK1:
Interrupt mask
flag registers 0, 1
INTM0: External
interrupt mode
register 0
INTM1: External
interrupt mode
register 1
Interrupt request
pending
Multiple interrupt
servicing
STOP mode
STOP mode,
HALT mode
STOP mode
OSTS:
Oscillation
stabilization time
select register
Details of
Function
−
No interrupt sources correspond to the vector table address 0014H.
Because P30, P31, P41, and P43 have an alternate function as external
interrupt inputs, when the output level is changed by specifying the output
mode of the port function, an interrupt request flag is set. Therefore, the
interrupt mask flag should be set to 1 before using the output mode.
Be sure to clear bits 0 and 1 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt
mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register,
clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag
(××MK× = 0), which will enable interrupts.
Be sure to clear bits 2 to 7 to 0.
Before setting INTM1, set PMK3 to 1 to disable interrupts.
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
Interrupt requests will be held pending while the interrupt request flag registers
0, 1 (IF0, IF1) or interrupt mask flag registers 0, 1 (MK0, MK1) are being
accessed.
Multiple interrupts can be acknowledged even for low-priority interrupts.
The LSRSTOP setting is valid only when “Can be stopped by software” is set
for the low-speed internal oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed internal oscillation clock).
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) and
bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D
conversion operation, and then execute the HALT or STOP instruction.
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 14-1).
To set and then release the STOP mode, set the oscillation stabilization time
as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization
time set by OSTS
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
18 OPTION BYTE.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17446EJ5V0UD
Cautions
p.226
pp.
229, 230
p.231
p.231
p.232
p.232
p.235
p.236
p.238
p.239
p.239
p.239
p.240
p.240
p.240
(14/20)
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