UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 402

• Manufacturer Part Number: UPD78F9234MC-5A4-A
• Description: MCU 8BIT 8KB FLASH 30PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9234MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

400
Serial
interface
UART6
Function
RXB6: Receive
buffer register 6
TXB6: Transmit
buffer register 6
ASIM6:
Asynchronous
serial interface
operation mode
register 6
ASIS6:
Asynchronous
serial interface
reception error
status register 6
Details of
Function
Reception enable status is entered, after having set RXE6 to 1 and one clock
of the base clock (f
When starting transmission, write transmit data to TXB6, after having set TXE6
to 1 and a wait of one clock or more of the base clock (f
performed.
Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface
transmission status register 6 (ASIF6) is 1.
Do not refresh (write the same value to) TXB6 by software during a
communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of
asynchronous serial interface operation mode register 6 (ASIM6) are 1 or
when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). When outputting
same values in continuous transmission, be sure to confirm that TXBF6 is 0
before writing the same values to TXB6.
At startup, transmission operation is started by setting TXE6 to 1 after having
set POWER6 to 1, then setting the transmit data to TXB6 after having waited
for one clock or more of the base clock (f
operation, set POWER6 to 0 after having set TXE6 to 0.
At startup, reception enable status is entered after having set POWER6 to 1,
then setting RXE6 to 1, and one clock of the base clock (f
When stopping reception operation, set POWER6 to 0 after having set RXE6
to 0.
Set POWER6 = 1 → RXE6 = 1 in a state where a high level has been input to
the RxD6 pin. If POWER6 = 1 → RXE6 = 1 is set during low-level input,
reception is started and correct data will not be received.
Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6
bits.
Fix the PS61 and PS60 bits to 0 when the interface is used in LIN
communication operation.
Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always
performed with “the number of stop bits = 1”, and therefore, is not affected by
the set value of the SL6 bit.
Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
The operation of the PE6 bit differs depending on the set values of the PS61
and PS60 bits of asynchronous serial interface operation mode register 6
(ASIM6).
The first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 6 (RXB6) but discarded.
Be sure to read ASIS6 before reading receive buffer register 6 (RXB6).
APPENDIX D LIST OF CAUTIONS
User’s Manual U17446EJ5V0UD
XCLK6
) has elapsed.
Cautions
XCLK6
). When stopping transmission
XCLK6
XCLK6
) has been
) has elapsed.
p.188
p.188
p.188
p.188
p.190
p.191
p.191
p.191
p.191
p.191
p.191
p.191
p.191
p.191
pp.
191, 209
(11/20)
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