SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 71

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

3.23
The On-Chip Debug Support of the TC1130 consists of the following building blocks:
• OCDS L1 module of TriCore™
• OCDS L2 interface of TriCore™
• OCDS L1 module in the BCU of the FPI Bus
• OCDS L1 facilities within the DMA
• OCDS L2 interface of DMA
• OCDS System Control Unit (OSCU)
• Multi Core Break Switch (MCBS)
• JTAG based Debug Interface (Cerberus JDI)
• Suspend functionality of peripherals
Features:
• TriCore™ L1 OCDS:
• DMA L1 OCDS:
• Level 2 trace port with 16 pins that outputs either TriCore™, or DMA trace
• OCDS System Control Unit (Cerberus OSCU)
• Multi Core Break Switch (Cerberus MCBS):
Figure 3-15
Data Sheet
– Hardware event generation unit
– Break by DEBUG instruction or break signal
– Full Single-Step support in hardware, possible also with software break
– Access to memory, SFRs, etc. on the fly
– Output break request on errors
– Suspension of pre-selected channels
– Minimum number of pins required (no OCDS enable pin)
– Hardware allows hot attach of a debugger to a running system
– System is secure (can be locked from internal)
– TriCore™, DMA, break pins, and BCUs as break sources
– TriCore™ as break targets; other parts can in addition be suspended
– Synchronous stop and restart of the system
– Break to Suspend converter
On-Chip Debug Support
shows a basic block diagram of the building blocks.
65
Functional Description
V1.1, 2008-12
TC1130