SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 162

• Manufacturer Part Number: SAK-TC1797-512F180E AC
• Description: IC MCU 32BIT FLASH 416-BGA
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1797-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000432392

5.3.6
Note: All PLL characteristics defined on this and the next page are not subject to
Table 20
Parameter
Accumulated jitter at
E_Ray module clock input
Accumulated jitter at
SYSCLK pin
VCO frequency range
VCO input frequency range
PLL base frequency
PLL lock-in time
1) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with
2) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with
3) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
f
f
the K factor after reset).
SAMPLE
SAMPLE
production test, but verified by design characterization.
not exceed
output pins, which can be loaded with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
V
V
frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
DDPF3
PP
DDPF
PP
= 80 MHz.
= 80 MHz.
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
E-Ray Phase Locked Loop (E-Ray PLL)
2)
at pin G23 and
at pin G24 and
PLL Parameters of the System PLL(Operating Conditions apply)
C
L
3)
= 20 pF with the maximum driver and sharp edge, except the E-Ray
1)
Symbol
D
D
f
f
f
t
V
VCO_ERAY
REF_ERAY
PLLBASE_ERAY
L_ERAY
V
P_ERAY_I
P_ERAY_E
SSOSC
SSOSC
at pin F25, is limited to a peak-to-peak voltage of
at pin F25, is limited to a peak-to-peak voltage of
158
Min.
–
–
400
20
140
–
C
L
= 25 pF. In case of applications with
Values
Typ. Max.
–
–
–
–
–
–
0.5
0.8
500
40
320
200
Electrical Parameters
V
V
PP
PP
f
f
OSC
OSC
= 40 mV for noise
= 40 mV for noise
Unit Note /
ns
ns
MHz –
MHz –
MHz –
µs
= 20MHz, K = 6, and
= 20MHz, K = 6, and
V1.1, 2009-04
Test Con
dition
–
–
–
TC1797